1. Field of the Invention
The present invention relates to a circuit simulation method for delay characteristic evaluation of a circuit in LSI (Large Scale Integration) and in particular relates to a method of performing simulation by simplifying the circuit and an associated program and device.
2. Description of the Related Art
As a method of evaluating delay characteristics in an integrated circuit, the method is known of dividing an integrated circuit into partial circuits and performing delay characteristic evaluation for each of the resulting partial circuits (called “target blocks”). As a method of dividing an integrated circuit into partial circuits, for example, the SCC (source-connected device clusters) boundary method may be employed in which, taking a drain of a transistor as a starting point, transistors or resistors that are connected with the power source or a gate are identified as source-connected device groups and division is effected using the gate input terminals as boundaries.
In this way, it is possible to perform delay characteristic evaluation by dividing out circuits (hereinbelow referred to as output load circuits) that are connected with the output-side terminals of the target blocks, in the same way as the target blocks were divided out, and combining these two and employing them in a simulation. This delay characteristic evaluation takes into account the output loads thereof as being the same as in the actual integrated circuit. However, if output load circuits are employed with the target blocks, the scale of the circuits used in the simulation tends to become large and information (various types of setting parameters and input data patterns) is required for simulation purposes not merely of the target blocks but also of the output load circuits.
If this is done, in cases where, for example, it is desired to specify the maximum delay based on the delay values in respect of all patterns of input data, the number of times that the simulation must be run and the time required for a single simulation are increased. Accordingly, simplifying (modeling) the output load circuits is executed for the scale of the simulation circuits to be decreased or for the amount of information required for the simulation to be reduced.
For example, modeling may be employed in which a transistor whose gate input terminal is the output terminal of the target block, and the parasitic capacitance thereof are divided out and the source and drain of the transistor that is thus divided out are short-circuited, or modeling may be employed in which a fixed potential is applied between the source and drain of the transistor that is thus divided out.
As related prior art, Laid-open Japanese Patent Application No. H11-296572 discloses a method of verifying the timing of a large-scale integrated circuit.